1. Field of the Invention
The invention relates to methods and devices for repairing a memory utilizing a Memory Built-In Self Repair (MBISR) structure.
2. Description of the Related Art
Digital memories typically consist of two-dimensional arrays of elements (storage cells) each capable of storing N different data values, where N is the number of stable states of the storage cell. The cells of the array are arranged into rows and columns.
Due to uncontrollable factors, memories may contain randomly distributed defective cells after fabrication which cause the memory to be unusable even if faults affect very small parts of the entire cell array. The larger the memory array, the lower the probability that the array is fault-free. Memory defects fall into four basic categories:                Clustered cell defects: defects affecting only one or few neighbouring cells.        Row defects: defects affecting multiple cells laying on the same row of the memory array.        Column defects: defects affecting multiple cells laying on the same column of the memory array.        Periphery defects: defects affecting the memory array periphery (sense amplifiers, IOs, output multiplexers etc.).        
To prevent most memories from being discarded after failing production tests due to scarcely distributed faults, groups of spare storage cells are provided which allow replacing the defective ones once they are detected. Generally, complex processing is required to identify optimal repair configurations; in addition, optimal repair configurations may not even be identified due to inefficient processing, thus leading to discarded memories which might be recovered instead.
Examples for state of the art methods for repairing a memory comprising a Memory Built-In Self Repair (MBISR) structure are described e.g. in Bhavsar, D. K.: “An Algorithm for Row-Column Self-Repair of RAMs and Its Implementation in the Alpha 21264”.—Preprint: Int'l Test Conference 1999, pp. 1 to 8, and in Kim, H. C. et al.: “A BISR (Built-In Self-Repair) circuit for embedded memory with multiple redundancies”.—IEEE 1999, pp. 602 to 605.
Classical repair strategies consist of replacing rows or columns for which at least one cell is defective. This simple criteria leads to excess waste of spare cells whenever the number of faulty cells in one row/column is significantly less than the total cells replaced.
New repair strategies are able to repair small groups of logically neighbouring cells (memory words) instead of complete rows and columns. Such word replacement is more flexible than row and column replacement in that it allows fixing sparse faulty cells, but it is not suitable for repairing column or periphery defects and, to some extent, row defects. Repair algorithms are not necessary for this type of redundancy, as words are replaced at testing run time after detection of faults.
Each state of the art solution (i.e. row/column and word oriented redundancy) can efficiently target only part of the above listed types of defects. To determine the optimal repair configuration, the data of all defective cells need to be stored for processing. In general, complex processing is required to identify the optimal repair configuration. The corresponding calculations are done either on or off chip.
Optimal repair configurations may not be identified due to inefficient processing, thus leading to discard memories which might be repaired instead.